High frequency power amplifier circuit

ABSTRACT

A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a multi-stage high-frequencypower amplifier circuit with a plurality of cascaded semiconductoramplifier devices and technology that is useful when applied to wirelesscommunication devices such as cellular phones incorporating ahigh-frequency power amplifier circuit, and more particularly to ahigh-frequency power amplifier circuit capable of obtaining output withdesired characteristics, independent of variations in semiconductoramplifier device characteristics.

[0002] The transmission output stage of car phones, cellular phones, andother wireless communication devices (mobile communication devices), asshown in FIG. 1, includes a multi-stage high-frequency power amplifiercircuit with cascaded semiconductor amplifier devices Q1, Q2, and Q3made of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors),GaAs-MESFETs (Metal Semiconductor Field-Effect Transistors), or otherapplicable kinds of transistors. The high-frequency power amplifiercircuit shown in FIG. 1 generally includes a discrete last-stagesemiconductor amplifier device Q3 (such as an output power MOSFET), andpreceding-stage semiconductor amplifier devices Q1 and Q2 and a biascircuit BIAS that are integrated onto a single semiconductor chip as asemiconductor integrated circuit. The combination of this discretesemiconductor amplifier device part and a semiconductor integratedcircuit including a bias circuit, together with capacitive elements andother circuit elements will be referred to as a high-frequency poweramplifier module or just as a module hereinafter.

[0003] In general, a cellular phone system is configured to change itsoutput (transmission power) in different communication environmentsaccording to power-level command signals from a base station, so as notto interfere with other cellular phones. For example, a high-frequencypower amplifier module in the transmission output stage of cellularphones adopting the U.S. 900-MHz band standard system or the EuropeanGSM (Global System for Mobile Communications) system is configured sothat the gate bias voltages of the output power MOSFETs Q1 to Q3 arecontrolled by the output voltage Vapc of an Automatic Power Control(APC) to produce the output power required for communication.

[0004] Conventionally, the gate bias voltages of the output powerMOSFETs are generated by using a bias circuit BIAS consisting ofresistance dividers as shown in FIG. 1, in which the output voltage Vapcof the APC circuit is divided by the ratios of paired resistances R11and R12, R21 and R22, and R31 and R32 to generate gate bias voltagesVg1, Vg2, and Vg3 (see, for example, Unexamined Japanese PatentPublication No. Hei 11(1999)-150483).

[0005] Some conventional systems, as shown in FIG. 2, use a bias circuitthat is configured with a plurality of resistances R1 to R4 connected inseries with a MOSFET Qd that functions as a diode, forming a resistivevoltage in which the ratio of the resistance values is adjusted so thatthe maximum output power can be obtained when Vapc is in the highneighborhood of 2 V, generating the gate bias voltages Vg1, Vg2, and Vg3of the output power MOSFETs in each stage (see, for example, UnexaminedJapanese Patent Publication No. 2001-102881).

[0006] As described above, all of the conventional gate bias circuitsabove apply bias voltages generated by dividing the output voltage Vapcof the APC circuit to the gates of the output power MOSFETs.

SUMMARY OF THE INVENTION

[0007] Output power MOSFETs show variations in threshold voltages due tomanufacturing process variations and temperature changes. In addition,the last-stage MOSFET Q3 among the output power MOSFETs, in particular,is often a discrete part. Therefore, the last-stage MOSFET Q3 andpreceding-stage MOSFETs Q1 and Q2 differ in regard to the variations inthe threshold voltage. More specifically, the gate voltage-drain currentcharacteristics of the output power MOSFETs are different from eachother.

[0008] In such a high-frequency power amplifier module configured withoutput power MOSFETs having different variations in their thresholdvoltages, if a gate bias voltage that is generated by dividing theoutput voltage Vapc of the APC circuit according to the ratio ofresistances is applied to the gate terminals of the output powerMOSFETs, the output characteristic of the high-frequency power amplifiercircuit may deviate greatly from a desired characteristic. As a result,a module with a bias circuit that generates gate bias voltage bydividing resistances requires fine tuning of the resistance valuesmaking up the bias circuit; this obviously creates a problem in thatextra trimming tasks or trimming resistors are required.

[0009] Accordingly, an object of the present invention is to provide ahigh-frequency power amplifier circuit capable of obtaining desiredcharacteristics without trimming the values of resistors making up thebias circuit.

[0010] Another object of the present invention is to provide ahigh-frequency power amplifier circuit with better outputcontrollability.

[0011] Another object of the present invention is to provide ahigh-frequency power amplifier circuit capable of efficiently obtaininghigher output with lower power consumption.

[0012] The aforementioned and other objects and new features of thepresent invention will become clear from the description in thisspecification when read with reference to the attached drawings.

[0013] The outline of a typical mode of practicing the inventiondisclosed herein will be described below.

[0014] In a multi-stage high-frequency power amplifier circuit with aplurality of cascaded output semiconductor amplifier devices Q1, Q2, andQ3, the invention typically provides semiconductor amplifier devicesQ11, Q12, and Q13 connected to the plurality of output semiconductoramplifier devices to form current mirror circuits respectively, causingelectric currents I11, I12, and I13 changing with given characteristicsaccording to control voltage to flow into the semiconductor amplifierdevices and driving the plurality of output semiconductor amplifierdevices with the currents.

[0015] The method described above drives the output semiconductoramplifier devices with currents having given characteristics, therebymaking it possible to obtain a high-frequency power amplifier circuitwith output characteristics not sensitive to possible variations in thethreshold voltages and other characteristics of the output semiconductoramplifier devices.

[0016] The semiconductor amplifier devices are preferably field effecttransistors, and the given characteristics are their gate voltage-draincurrent characteristics. Since the drain current of a field effecttransistor is proportional to the square of the gate voltage, thecontrol voltage can reduce the rate of change of the output in thevicinity of the threshold voltage of the field effect transistor andincrease the rate of change of the output by increasing itself, therebymaking it possible to achieve higher output controllability and largeroutput power.

[0017] According to another aspect of the invention disclosed herein, ina high-frequency power amplifier circuit having a multi-stage outputcircuit with a plurality of cascaded semiconductor amplifier devices Q1,Q2, and Q3 and a bias circuit that drives the semiconductor amplifierdevices responsive to a control voltage, the invention providessemiconductor amplifier devices Q11, Q12, and Q13 that are connected tothe plurality of output semiconductor amplifier devices so as to formcurrent mirror circuits; the bias circuit has a voltage-to-currentconverter 10, a first resistance R1 that converts currents I1 and I3supplied from the voltage-to-current converter, a first constant-currentsource 31, and a first semiconductor amplifier device Q32 connected inseries thereto; also included is a control voltage generator 30 thatgenerates a voltage equal to the threshold voltage of the firstsemiconductor amplifier device; a second semiconductor amplifier deviceQ21 (Q31) generates current according to a combination of the voltagegenerated by the control voltage generator and the voltage converted bythe first resistance; and currents I11, I12, and I13 with the samecharacteristic as that of current I21 flowing through the secondsemiconductor amplifier device are passed through the semiconductoramplifier devices connected to the plurality of output semiconductoramplifier devices in pair respectively so as to form the current mirrorcircuits to drive the plurality of output semiconductor amplifierdevices.

[0018] Preferably, the control voltage generator has a voltage follower33 including a first differential circuit that receives a voltage equalto the threshold voltage of the first semiconductor amplifier device;the first resistance R1 is connected to the output terminal of thevoltage follower; and currents I1 and I3 fed from the voltage-to-currentconverter via the first resistance are caused to flow through thevoltage follower. This enables the voltage follower, which has smalloutput impedance, to sink sufficient currents I1 and I3 supplied fromthe voltage-to-current converter and generate a voltage proportional tothe currents I1 and I3 supplied from the voltage-to-current converterthrough the first resistance to be applied to the control terminal ofthe second semiconductor amplifier device to produce current.

[0019] More preferably, second constant-current sources 21 a and 21 cthat are connected to the control terminals of the second semiconductoramplifier devices and sink current supplied from the voltage-to-currentconverter are provided. This can produce an initial control voltage atwhich the current passing through the second semiconductor amplifierdevices starts to change, thereby making it easier to obtain a desiredcurrent characteristic.

[0020] The first constant-current source 31 is configured to include asecond differential circuit 312 receiving a constant voltage as an inputfrom a band gap reference circuit 311 that generates a constant voltageand a third semiconductor amplifier device Q30 that carries constantcurrent from the output of the second differential circuit. This canmake the current characteristic of the first output semiconductoramplifier device constant regardless of variations in the power sourcevoltage.

[0021] In addition, the second differential circuit 312 has its outputfed back to the other input through a circuit including an amplifierdevice Q44 and a second resistance R4. This feedback causes the seconddifferential circuit to output a voltage Vc1 proportional to theconstant voltage Vref from the output terminal. The third semiconductoramplifier device Q30 forms a current mirror with the amplifier deviceQ44 to pass a current responsive to the value of the second resistanceR4 as a constant current I4. The second resistance R4 is constituted byan external device. Since an external device can be provided with higheraccuracy than a device integrated on a chip, using it can improveoperation accuracy of the circuit.

[0022] In addition, the second constant-current source 21 a (21 c) isconfigured to include a third differential circuit 321 that receives aconstant voltage (Vref) as an input from the band gap reference circuit311, which generates a constant voltage with little dependecy on thepower source voltage, and a fourth semiconductor amplifier device Q31that carries constant current responsive to the output Vc2 of the thirddifferential circuit. This makes it possible to provide the first outputsemiconductor amplifier device with a constant current characteristicindependent of variations in the power source voltage.

[0023] The output of the third differential circuit 321 is fed back tothe other input via a circuit including an amplifier device Q45 and athird resistance R5. This feedback causes the third differential circuitto output a voltage Vc2 proportional to the constant voltage Vref fromthe output terminal. The fourth semiconductor amplifier device Q31constitutes a current mirror with the amplifier device Q45 and isconfigured to pass current responsive to the value of the thirdresistance R5 as a constant current I5 a (I5 c); the third resistance R5is formed integrally with the first to fourth semiconductor amplifierdevices in the same semiconductor chip. When the output currents I1 andI3 vary due to manufacturing process variations in the value of theresistance R2 provided in the voltage-to-current converter 10, thisconfiguration causes the same variation in the value of the thirdresistance R5 as in the resistance R2 in the voltage-to-currentconverter, which causes a current I5 a (I5 c) to change, therebyenabling the changes in the output currents I1 and I3 to be canceled.

[0024] Furthermore, the first resistance, the second semiconductoramplifier device, and the second current source are provided for each ofthe plurality of the output semiconductor amplifier devices; theresistance value of the first resistance and the current value of thesecond current source are set to mutually differing values. This enablesseparate control with desired characteristics of the plurality of outputsemiconductor amplifier devices, thereby making it possible to achieve ahigh-frequency power amplifier circuit with better outputcontrollability and capable of efficiently obtaining higher output withlower power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a circuit diagram showing an example of a conventionalmulti-stage high-frequency power amplifier circuit;

[0026]FIG. 2 is a circuit diagram showing another example of a biascircuit provided in a conventional high-frequency power amplifiercircuit;

[0027]FIG. 3 is a circuit diagram showing an embodiment of ahigh-frequency power amplifier circuit according to the presentinvention;

[0028]FIG. 4 is a graph showing relations between a control voltage Vapcin a bias circuit and a gate voltage of a bias-current generating MOSFETin the high-frequency power amplifier circuit according to the presentinvention;

[0029]FIG. 5 is a graph showing relations between a control voltage Vapcin the bias circuit and a drain current of the bias-current generatingMOSFET in the high-frequency power amplifier circuit according to thepresent invention;

[0030]FIG. 6 is a circuit diagram showing a specific example of avoltage-to-current converter that converts a control voltage Vapc to acurrent supplied to the bias circuit;

[0031]FIG. 7 is a circuit diagram showing a specific example of aconstant voltage circuit that generates a constant voltage independentof a power source voltage;

[0032]FIG. 8 is a circuit diagram showing a specific example of aconstant voltage circuit that generates a constant voltage that cancelsvariations in current output from the voltage-to-current converter;

[0033]FIG. 9 is a circuit block diagram showing a part of a cellularphone including the high-frequency power amplifier circuit shown in FIG.3; and

[0034]FIG. 10 is a block diagram showing the entire structure of acellular phone using the high-frequency power amplifier circuitaccording to the embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Preferable embodiments of the present invention will be describedwith reference to the attached drawings below. Although the followingdescription will use a field effect transistor (FET) as an example of asemiconductor amplifier device, the semiconductor amplifier device isnot limited to a field effect transistor; it may be a bipolartransistor, hetero-junction bipolar transistor (HBT),high-electron-mobility transistor (HEMT), or another applicable kind oftransistor; a semiconductor substrate forming a transistor is notlimited to a silicon substrate; it may also be a silicon-germanium orgallium-arsenic substrate, or one made of another applicable material.

[0036]FIG. 3 shows an embodiment of a high-frequency power amplifiercircuit according to the present invention. In FIG. 3, Q1, Q2, and Q3indicate output power MOSFETs used as output transistors; these outputpower MOSFETs Q1, Q2, and Q3 are interconnected so that the drainterminal of the preceding-stage FET is connected to the gate terminal ofthe next-stage FET via capacitive elements C1 and C2. The gate terminalof the first-stage output power MOSFET Q1 receives a radio-frequencysignal RFin via a capacitive element C0; the drain terminal of thelast-stage output power MOSFET Q3 is connected to an output terminal OUTvia a capacitive element C3, eliminates the direct-current components ofthe radio-frequency signal Rfin, amplifies only the alternate-currentcomponents, and outputs the resultant signal. The output power at thistime is controlled by the bias circuit described below.

[0037] This embodiment provides MOSFETs Q11, Q12, and Q13 paired inparallel with the output power MOSFETs Q1, Q2, and Q3, their drainsbeing connected to the gates of the output power MOSFETs Q1, Q2, and Q3respectively to provide a diode function; the gates of MOSFETs Q11, Q12,and Q13 are connected with the gates of the output power MOSFETs Q1, Q2,and Q3, thereby forming current mirror circuits.

[0038] In the high-frequency power amplifier circuit shown in FIG. 3,the last-stage output power MOSFET Q3 and MOSFET Q13 forming a currentmirror circuit with Q3 are formed onto a single semiconductor chip as adiscrete part; the preceding-stage output power MOSFETs Q1 and Q2 andMOSFETs Q11 and Q12 paired with them respectively to form current mirrorcircuits, and a bias circuit that feeds bias current to MOSFETs Q11 toQ13 are formed on another single semiconductor chip as a semiconductorintegrated circuit. The capacitive elements C0, C1, C2, and C3 arediscrete parts, connected to the semiconductor integrated circuitincluding the bias circuit as external devices.

[0039] The bias circuit includes a voltage-to-current converter 10 thatoutputs currents I1 and I3 proportional to a control voltage Vapc;current generators 20A, 20B, and 20C that generate currents with desiredcharacteristics little depencency on thresholds, based on the currentsI1 and I3, and feed the currents to the MOSFETs Q11, Q12, and Q13 forforming the current mirror circuits; and a gate voltage control circuit30 that generates a bias voltage for these current generators 20A, 20B,and 20C and causes the current generators 20A, 20B, and 20C to outputcurrents with given characteristics.

[0040] The current generators 20A and 20C have the same circuitconfiguration. Although not limited to this, this embodiment has astructure in which the current generator 20B that generates current I12fed to the MOSFET Q12 connected to the second-stage output power MOSFETQ2 to form a current mirror circuit includes a MOSFET Q20 connected toan output MOSFET Q22 of the current generator 20A to form a currentmirror circuit, and the MOSFET Q20 generates current I12 having the samecharacteristic as that of the current I11 fed from the current generator20A to the MOSFET Q11. The ratio of currents I11 and I12 can be adjustedby changing the size ratio of MOSFETs Q22 and Q20.

[0041] The gate voltage control circuit 30 includes a constant-currentsource 31; a MOSFET Q32 connected to the constant-current source 31 inseries; and a differential amplifier 33 that receives a drain voltage ofthe MOSFET Q32 to behave as a voltage follower. The MOSFET Q32 with itsgate and drain connected to function as a diode outputs a voltage equalto the threshold voltage Vgsl from the drain terminal to thedifferential amplifier 33; the differential amplifier 33 outputs avoltage at the same level as that of the input voltage, or at the samelevel as that of the threshold voltage Vgsl of the MOSFET Q32.

[0042] The current generator 20A includes a source-follower MOSFET Q21;a resistance R1 inserted between the gate terminal of the MOSFET Q21 andthe output terminal of the differential amplifier 33 in the gate voltagecontrol circuit 30; a constant-current source 21 a that is connectedbetween the gate terminal of the MOSFET Q21 and ground and passesconstant current I5 a; a MOSFET Q22 inserted in series between the drainterminal of the MOSFET Q21 and a power source voltage terminal Vdd; anda MOSFET Q23 with the gate terminal connected to the gate of the MOSFETQ22 to form a current mirror circuit.

[0043] The termination of the wiring for supplying current I1 responsiveto the control voltage Vapc output from the voltage-to-current converter10 is linked to a connection node n1 of the resistance R1 and the gateterminal of the MOSFET Q21. This causes the current I1 from thevoltage-to-current converter 10 to be distributed to theconstant-current source 21 a and the output terminal of the differentialamplifier 33 if I1 is larger than I5 a (I1>I5 a), and to be fed all tothe constant-current source 21 a if I1 is smaller than I5 a (I1<I5 a).If I1 is smaller than I5 a (I1<I5 a), current with a value equal to I5a−I1 flows from the output terminal of the differential amplifier 33toward the constant-current source 21 a via the resistance R1.

[0044] The operations of the current generator 20A will be describedbelow.

[0045] First, suppose the current generator 20 a without theconstant-current source 21 a. Current I1 from the voltage-to-currentconverter 10 flows through the resistance R1 and the output terminal ofthe differential amplifier 33 into the differential amplifier. Theoutput voltage of the differential amplifier 33 is at the same level ofthat of the threshold voltage Vgsl of the MOSFET Q32 as described above.Therefore, the gate voltage VG2 is higher than the output voltage Vgslof the differential amplifier 33 by R1·I1, or Vgsl+Rl·I1. The current I1fed from the voltage-to-current converter is proportional to the controlvoltage Vapc as described above.

[0046] Therefore, the gate voltage VG2 of the MOSFET Q21 varies almostlinearly with the control voltage Vapc, as indicated by line A shown inFIG. 4. Then, the current I21 flowing through the MOSFET Q21 variesaccording to the drain current characteristic of the MOSFET responsiveto the control voltage Vapc, as indicated by curve a shown in FIG. 5.Since the MOSFETs Q32 and Q21 are formed on a single semiconductor chip,the amounts of variation in their threshold voltages are the same.Specifically, as the threshold voltage of Q32 increases, the thresholdvoltage of Q21 increases by the same amount; as the threshold voltage ofQ32 decreases, the threshold voltage of Q21 also decreases by the sameamount.

[0047] As a result, the current I21 flowing into the MOSFET Q21 varieswith a given characteristic regardless of the variations in thethreshold voltage. Then the current I21 is passed through two currentmirror circuits formed by the pairs of MOSFETs Q22 and Q23 and MOSFETsQ11 and Q1 to the output power MOSFET Q1. Therefore, the output powerMOSFET Q1 carries a current with the same characteristic as the draincurrent characteristic of the MOSFET Q21. More specifically, even if thethreshold voltage of the MOSFET Q1 deviates from a desired value due tomanufacturing process variations and temperature changes, an outputcharacteristic independent thereof can be obtained.

[0048] On the other hand, considering a case in which theconstant-current source 21 a is provided and current I5 a flows therein,since the current I5 a reduces a current flowing from thevoltage-to-current converter 10 into the differential amplifier 33 viathe resistance R1, the gate voltage VG2 of MOSFET Q21 isVgs1+R1·I1−R1·I5 a. Specifically, when the constant-current source 21 ais provided, the gate voltage VG2 of the MOSFET Q21 can be plotted byline B in FIG. 4, which is line A shifted downward by R1·I5 a.

[0049] The current I5 a flowing into the constant-current source 21 a iskept constant regardless of the control voltage Vapc. The current I1 fedfrom the voltage-to-current converter 10 is proportional to the controlvoltage Vapc. Therefore, the slope of line B is the same as that of lineA. This causes the current I21 flowing through the MOSFET Q21 variesresponsive to the control voltage Vapc along curve b in FIG. 5. Theslopes of lines A and B shown in FIG. 4 can be adjusted by the value ofthe resistance R1, and can be reduced by reducing the value of theresistance R1, thus the controllability of the output power MOSFETs Q1to Q3 by a control voltage Vapc can be improved.

[0050] The current generator 20C, as is the case with the currentgenerator 20A, includes a source-follower MOSFET Q31; a resistance R3inserted between the gate terminal of the MOSFET Q31 and the outputterminal of the differential amplifier 33 in the gate voltage controlcircuit 30; a constant-current source 21 c that is connected between thegate terminal of the MOSFET Q31 and ground and passes a constant currentI5 c; a MOSFET Q32 inserted between the drain terminal of the MOSFET Q31and the power source voltage terminal Vdd in series; and a MOSFET Q33with the gate terminal connected to the gate terminal of the MOSFET Q32to form a current mirror circuit. The values of a current I5 c flowingthrough the constant-current source 21 c and the resistance R3 are setto values different from the values of a current I5 a flowing throughthe constant-current source 21 a in the current generator 20A and theresistance R1.

[0051] This causes the gate voltage VG3 of the MOSFET Q31 variesaccording to line C in FIG. 4, for example. As a result, the draincurrent, or the bias current I13 flowing in the current mirror circuitformed by the pair of MOSFETs Q13 and Q3 has a characteristic indicatedby curve c in FIG. 5. Optimal setting of the values of the current I5 cflowing through the constant-current source 21 c in the currentgenerator 20B and the resistance R3, and the values of the current I5 aflowing through the constant-current source 21 a in the currentgenerator 20A and the resistance R1 makes it possible to obtain largeroutput with a smaller operating current.

[0052] The bias circuit according to the embodiment shown in FIG. 1configures the current generator 20B that generates a bias current forthe second-stage output MOSFET Q2 only with the MOSFET Q20 connected tothe MOSFET Q22 in the current generator 20A to form a current mirror,but it is also possible to configure the current generator 20B in thesame way as with the current generator 20A and appropriately set thevalues of a current flowing through a current source equivalent to theconstant-current source 21 a and a resistance equivalent to theresistance R1 according to the output MOSFETs Q1 to Q3 used therein,thereby obtaining a desired characteristic for the entire module.

[0053]FIG. 6 shows a specific example of the voltage-to-currentconverter 10 that generates currents I1 and I3 fed to the currentgenerators 20A and 20C based on a control voltage Vapc.

[0054] The voltage-to-current converter 10 of this embodiment includes adifferential amplifier 11 configured with a CMOS differential amplifiercircuit that receives a control voltage Vapc as an input; MOSFETs Q41,Q42, and Q43 with the gate terminals to which a potential at theinverting output node of the differential amplifier 11 is applied; and aresistance R2 that is connected to the MOSFET Q41 in series: in which apotential at the connection node of the MOSFET Q41 and the resistance R2is fed back to the other input terminal of the differential amplifier11, whereby a drain current proportional to the input voltage Vapc isfed to each of the MOSFETs Q42 and Q43. The value of the drain currentto the MOSFETs Q42 and Q43 can be set arbitrarily according to the sizeratio (gate width W ratio) of the MOSFETs Q41 and Q42 and the value ofthe resistance R2 and the size ratio of the MOSFETs Q41 and Q43 and thevalue of the resistance R2, which is output as currents I1 and I3 fed tothe current generators 20A and 20C respectively.

[0055]FIG. 7 shows a specific example of a constant-current circuit asthe constant-current source 31 that constitutes the gate voltage controlcircuit 30. The constant-current source 31 of this embodiment includes aband gap reference circuit 311 that generates a reference voltage Vrefwith little dependency on the power source; a differential circuit 312receives a reference voltage Vref from the band gap reference circuit311 as an input at one of its input terminals; a MOSFET Q44 thatreceives the output of the differential circuit 312 at the gateterminal; a resistance R4 inserted between the MOSFET Q44 and ground;and MOSFET Q30 that receives the output voltage Vc1 of the differentialcircuit 312 at the gate terminal: in which feedback is carried out fromthe point of interconnection of the MOSFET Q44 and the resistance R4 tothe other input terminal of the differential circuit 312.

[0056] In the constant-current source 31 shown in FIG. 7, the output ofthe differential circuit 312 is fed back to the other input terminalthereof through a circuit including the MOSFET Q4 and the resistance R4.This makes it possible to obtain a constant voltage Vc1 responsive tothe value of the resistance 4 from the output terminal of thedifferential circuit 312. Since the constant voltage Vc1 is alsosupplied to the gate of the MOSFET Q30, the MOSFET Q30 forms a currentmirror in combination with the MOSFET Q44. Therefore, the MOSFET Q30passes a current responsive to the value of the resistance R2 as acurrent I4. This embodiment uses an external resistive element as theresistance R2. This provides a configuration capable of outputting acurrent I4 with higher accuracy than obtainable with a resistance formedon the chip.

[0057]FIG. 8 shows a specific example of a constant-current circuit asthe constant-current source 21 a (21 c) that constitutes the currentgenerator 20A (20C). The constant-current source 21 a (21 c) of thisembodiment includes a differential circuit 321 that receives a referencevoltage Vref output from a band gap reference circuit 311 shared withthe constant-current source 31 as an input at one of the inputterminals; a MOSFET Q45 that receives the output of the differentialcircuit 321; a resistance R5 inserted between the MOSFET Q45 and ground;a MOSFET Q31 that receives the output voltage Vc2 of the differentialcircuit 321 at the gate terminal; a MOSFET Q32 that is connected to theMOSFET Q31 in series; and a MOSFET Q33 that is connected to the Q32 toform a current mirror: in which feedback is carried out from the pointof interconnection of the MOSFET Q45 and the resistance R5 to the otherinput terminal of the differential circuit 312.

[0058] In the constant-current circuit 21 a (21 c) shown in FIG. 8, theoutput of the differential circuit 321 is fed back to the input terminalvia a circuit including the MOSFET Q45 and the resistance R5. This makesit possible to obtain a constant voltage Vc2 responsive to the value ofthe resistance R5 from the output terminal of the differential circuit321. Since the constant voltage Vc2 is also supplied to the gateterminal of the MOSFET Q31 that constitutes a current mirror incombination with the MOSFET Q45, the current responsive to the value ofthe resistance R5 flows through MOSFET Q31. The circuit is configured sothat the drain current flowing in the MOSFET Q31 is copied by MOSFETsQ32 and Q33 that form a current mirror circuit in pair and a constantcurrent I5 a (I5 c) flows through the MOSFET Q33.

[0059] Unlike the constant-current source 31 that passes the constantcurrent I4 shown in FIG. 7, the constant-current source of thisembodiment employs a resistance formed on the chip as the resistance R5,rather than an external device. When the output currents I1 and I3change due to manufacturing process variations of the resistance R2provided in the voltage-to-current converter 10 shown in FIG. 6, thisconfiguration causes the same variation in the value of the resistanceR5 that constitutes the constant-current source 21 a (21 c) shown inFIG. 8 as in the resistance R2, which causes an output current I5 a tochange, thereby enabling the changes in the output current I1 and I3 fedfrom the voltage-to-current converter 10 to be cancelled.

[0060] The differential circuits 312 and 321, although not limited tothis configuration, include a pair of differential transistors Qp1 andQp2, current mirror transistors Qc1 and Qc2 that constitute the loadcircuits thereof, and a constant current device I.

[0061]FIG. 9 is a block diagram showing a portion of a cellular phoneincorporating the high-frequency power amplifier circuit shown in FIG.3.

[0062] In this cellular phone, as shown in FIG. 9, an RF transmissionsignal generated by oscillating operations of a modulation oscillator(VCO) 70 is input to the input terminal (Pin) of a high-frequency poweramplifier module 1. The RF transmission signal is amplified in thehigh-frequency power amplifier module 1 and output from the outputterminal (Pout), then transmitted through a power detector 71 andtransmission filter 72 to an antenna 73, and transmitted as a radio wavetherefrom.

[0063] On the other hand, an RF receive signal is subject to signalprocessing in a receiver circuit 80. The receiver circuit 80 outputs areceived signal strength indication signal SRI, which is converted to adigital signal in an A/D converter 81 and supplied to a control logic82. The control logic 82 outputs a power-level command signal SPL, whichis supplied to a control logic circuit 84 in an output level controller83. The control logic circuit 84 processes the received power-levelcommand signal SPL to generate a control code, and the generated controlcode is converted to an analog signal in a D/A converter 85, which issupplied to the automatic power control (APC) circuit 74 as a powerlevel command voltage VPL. The APC circuit 74 forms a power controlsignal Vapc responsive to the power level command voltage VPL andsupplies it to the high-frequency power amplifier module 1, which drivesan output transistor in response to this signal. Reference numeral 90indicates a battery that supplies a power source voltage Vdd to thehigh-frequency power amplifier module 1.

[0064]FIG. 10 is a block diagram showing the entire structure of acellular phone using the high-frequency power amplifier circuit of theembodiment.

[0065] The cellular phone of this embodiment includes a liquid crystalpanel 200 as a display unit; an antenna 321 for transmitting andreceiving signals; a voice output speaker 322; a voice input microphone323; a liquid crystal control deriver 310 that drives the liquid crystalpanel 200 to provide a display; an audio interface 330 that inputs andoutputs signal for the speaker 322 and the voice input microphone 323; ahigh-frequency interface 340 that makes a GSM-system cellular phonecommunication via the antenna 321; a Digital Signal Processor (DSP) 351that performs signal processing of voice signals and transmitting andreceiving signals; an Application Specific Integrated Circuits (ASIC)352 that provides custom functions (user logic); a system controller 353including a micro processor or micro computer that controls the entiresystem including display control; a memory unit 360 for storing data andprograms; an oscillator (OSC) 370; and other components. The DSP 351,ASIC 352, and micro computer 353 as a system controller constitute aso-called base band unit 350. The high-frequency power amplifier circuitof the embodiment above is employed in the transmission output unit ofthe high-frequency interface 340.

[0066] Although the invention has been described above in its preferredembodiments, it is needless to say that the invention is not limited tothe specific embodiments described above and various changes may be madewithout departing from the spirit or scope of the invention. Forexample, the embodiments use three-stage output transistors, but itallows use of two-stage or four- or -more-stage structure. In addition,although it has been described that the last-stage output transistor Q3and the transistor Q3 connected thereto to form a current mirror circuitare formed in a discrete chip, they may be formed together with theother output transistors Q1 and Q2 in the same chip as the one with thebias circuit, or in contrast, the output transistor Q1 and the currentmirror transistor Q11 or the output transistor Q2 and the current mirrortransistor Q12 may also be formed in a discrete chip.

[0067] Although the invention made by the inventors has been describedabove mainly in relation to a high-frequency power amplifier circuitapplied in wireless communication devices, the invention is not limitedto this field, but may be widely applied to multi-stage amplifiercircuits with a plurality of cascaded semiconductor amplifier devicesand systems including such circuits.

[0068] The outline of a typical mode of practicing the inventiondisclosed herein will be described below.

[0069] Specifically, since the output transistors are driven withcurrents having desired characteristics responsive to a control voltage,it is possible to obtain a high-frequency power amplifier circuit withoutput characteristics not sensitive to possible variations in thethreshold voltages of the output transistors. In addition, driving anoutput transistor at each stage with a separate bias current makes itpossible to achieve a high-frequency power amplifier circuit with betteroutput controllability and capable of efficiently obtaining higheroutput with lower power consumption.

What is claimed is:
 1. A high-frequency power amplifier circuit with aplurality of cascaded semiconductor amplifier devices, comprisingsemiconductor amplifier devices each making up a current mirror circuitwith each of the plurality of semiconductor amplifier devices; whereinthe semiconductor amplifier devices receive currents that vary withgiven characteristics according to a control voltage, and the pluralityof semiconductor devices are driven by the currents.
 2. Thehigh-frequency power amplifier circuit according to claim 1, wherein thesemiconductor devices are field-effect transistors and the givencharacteristics are gate voltage-drain current characteristics of thefield-effect transistors.
 3. A high-frequency power amplifier circuitcomprising: an output circuit with a plurality of cascaded semiconductordevices; a bias circuit that drives the semiconductor amplifier devicesaccording to a control voltage; and semiconductor devices that arearranged so as to construct current mirror circuits with the pluralityof semiconductor amplifier devices, wherein the bias circuit includes avoltage-to-current converter that converts a control voltage to current;a first resistance for converting current supplied from thevoltage-to-current converter to a voltage; a first current source; afirst semiconductor amplifier device connected to the first currentsource in series; a control voltage generator that generates a voltageequal to the threshold voltage of the first semiconductor amplifierdevice; and a second semiconductor amplifier device that generatescurrent responsive to the combination of a voltage generated in thecontrol voltage generator and a voltage converted by the firstresistance, wherein a current with a characteristic responsive tocurrent flowing into the second semiconductor amplifier device issupplied to the semiconductor devices arranged so as to form the currentmirror circuits, and the semiconductor amplifier device is driven by thecurrent.
 4. The high-frequency power amplifier circuit according toclaim 3, wherein the control voltage generator has a voltage followerthat receives a voltage equal to the threshold voltage of the firstsemiconductor amplifier device, the output terminal of the voltagefollower is connected to the first resistance, and current is suppliedto the voltage follower from the voltage-to-current converter via thefirst resistance.
 5. The high-frequency power amplifier circuitaccording to claim 4, further comprising a second current source that isconnected to the control terminal of the second semiconductor amplifierdevice and sinks current supplied from the voltage-to-current converter.6. The high-frequency power amplifier circuit according to claim 5,wherein the first power source has a differential circuit that receivesconstant voltage from a constant-voltage circuit as an input and a thirdsemiconductor amplifier device that passes a constant current accordingto the output voltage of the differential circuit.
 7. The high-frequencypower amplifier circuit according to claim 6, wherein the differentialcircuit has an output connected to the gate terminal of an amplifierdevice arranged so as to form a current mirror circuit with the thirdsemiconductor amplifier device, the second resistance is connected tothe amplifier device in series, the differential circuit outputs voltageproportional to the constant voltage when a potential at the point ofinterconnection of the amplifier device and the second resistance is fedback to the input terminal of the differential circuit, the thirdsemiconductor amplifier device is driven by the voltage output from thedifferential circuit to carry constant current, and the secondresistance is an external device.
 8. The high-frequency amplifiercircuit according to claim 7, wherein the second current source has asecond differential circuit that receives a constant voltage from theconstant-voltage circuit as an input and a fourth semiconductoramplifier device that supplies constant current according to the outputof the second differential circuit.
 9. The high-frequency amplifiercircuit according to claim 8, wherein the second differential circuithas an output connected to the gate terminal of the amplifier devicethat is arranged so as to form a current mirror circuit with the fourthsemiconductor amplifier device; a third resistance is connected to theamplifier device in series, the second differential circuit outputs avoltage proportional to the constant voltage when a potential at thepoint of interconnection of the amplifier device and the thirdresistance is fed back to the input terminal of the second differentialcircuit, the fourth semiconductor amplifier device is driven by thevoltage output from the second differential circuit to carry constantcurrent, and the third resistance and the first to fourth semiconductoramplifier devices are formed on the same semiconductor chip.
 10. Thehigh-frequency power amplifier circuit according to claim 9, wherein thefirst resistance, the second semiconductor amplifier device, and thesecond current source are provided corresponding to each of theplurality of the semiconductor amplifier devices, a resistance value ofthe first resistance provided corresponding to each of the plurality ofthe semiconductor amplifier devices and a current value of the secondcurrent source provided corresponding to each of the plurality of thesemiconductor amplifier devices are set to mutually differing values.